A memory element is a widely used digital circuit and occurs, for instance, as a latch implemented with two cross-coupled inverters, or as an arbiter (temporal priority decoder) implemented with cross-coupled NAND gates or NOR gates that supply an output signal indicative of which of a plurality of input signals was the first one to arrive at an input of the arbiter.
In digital circuitry a signal has to assume one of two logic values in order to be processed correctly. Therefore, any in-between signal value should be avoided during a time span that is sufficiently long for a receiving circuit to react thereon. A reaction by the receiving circuit on a signal with an in-between value would lead to ambiguous circuit states and erroneous data processing.
A common problem with digital memory elements is that they are often unavoidably given ambiguous control signals. For example, an arbiter might be asked to tell which of two simultaneous signals arrived first, or a latch might be asked to store data which is in transition. This leads to what is commonly referred to as a metastable state, in which the memory element is balancing at a point of unstable equilibrium.
The behavior of such a cross-coupled device with regard to its immunity against staying in an indeterminable state can be visualized with the help of the following thought experiment. Initially, outputs of the device will be interconnected in order to let the circuit settle at a trip-point of the cross-coupled device. Thereupon the outputs are to be disconnected in order to let the element resolve into one of its logic states. The time it takes to settle into a logic state is a measure of the circuit's immunity to such metastable states: the shorter this time, the better its immunity.
In view of the ever decreasing signal propagation times in VLSI-circuits due to higher clock rates and smaller datapath features, this settling time should be as short as possible. Cross-coupling the logic gates through comparatively large output buffers located at the output of each logic gate would indeed increase the driving force of each. However, each buffer would also entail a higher capacitance to be charged or discharged and therefore to a longer settling time. Alternatively, increasing the transistors, sizes in each gate would indeed lead to larger currents to charge and discharge the gates, output nodes. However, this advantage would be offset by the increased capacitive load at these nodes due to the larger transistors.